The present invention relates to silicon-based field emitter tips and, in particular, to a method for sharpening silicon-based field emitter tips at low temperatures.
The present invention relates to design and manufacture of field emitter tips, including silicon-based field emitter tips. A brief discussion of field emission and the principles of design and operation of field emitter tips is therefore first provided in the following paragraphs, with reference to FIG. 1.
When a wire, filament, or rod of a metallic or semiconductor material is heated, electrons of the material may gain sufficient thermal energy to escape from the material into a vacuum surrounding the material. The electrons acquire sufficient thermal energy to overcome a potential energy barrier that physically constrains the electrons to quantum states localized within the material. The potential energy barrier that constrains electrons to a material can be significantly reduced by applying an electric field to the material. When the applied electric field is relatively strong, electrons may escape from the material by quantum mechanical tunneling through a lowered potential energy barrier. The greater the magnitude of the electrical field applied to the wire, filament, or rod, the greater the current density of emitted electrons perpendicular to the wire, filament, or rod. The magnitude of the electrical field is inversely related to the radius of curvature of the wire, filament, or rod.
FIG. 1 illustrates principles of design and operation of a silicon-based field emitter tip. The field emitter tip 102 rises to a very sharp point 104 from a silicon-substrate cathode 106, or electron source. A localized electric field is applied in the vicinity of the tip by a first anode 108, or electron sink, having a disk-shaped aperture 110 above and around the point 104 of the field emitter tip 102. A second cathode layer 112 is located above the first anode 108, also with a disk-shaped aperture 114 aligned directly above the disk-shaped aperture 110 of the first anode layer 108. This second cathode layer 112 acts as a lens, applying a repulsive electronic field to focus the emitted electrons into a narrow beam. The emitted electrons are accelerated towards a target anode 118 impacting in a small region 120 of the target anode defined by the direction and width of the emitted electron beam 116. Although FIG. 1 illustrates a single field emitter tip, silicon-based field emitter tips are commonly micro-manufactured by microchip fabrication techniques as regular arrays, or grids, of field emitter tips.
Silicon-based field emitter tips are commonly located on the surface of complementary metal-oxide semiconductor (xe2x80x9cCMOSxe2x80x9d) wafers. As discussed above, the current density of emitted electrons from a field emitter tips greatly increases with a decrease in the radius of the tip. Therefore, since it is desirable to achieve high current densities from silicon-based field emitter tips, tip sharpening procedures are normally employed in the final stage or stages of silicon-based field emitter tip array manufacture. FIGS. 2A-C illustrate a currently-available tip-sharpening procedure. In FIG. 2A, a blunt silicon-based field emitter tip 202 rises from a flat silicon substrate 204. In order to sharpen the tip, a thin surface layer of the field emitter tip and silicon substrate is heated to thermally oxidize silicon to SiO2. FIG. 2B shows the field emitter tip shown in FIG. 2A following thermal oxidation. The thin SIO2 layer 206 is grown inward from the surface of the field emitter tip and silicon substrate to produce a sharp, silicon-based field emitter tip 208 embedded within the thin SiO2 coating 206. Finally, the thin S102 layer is removed by hydrofluoric acid, HF, wet etching. FIG. 2C shows the final sharp field emitter tip following HF wet etching. The point 210 of the final sharp field emitter tip may have a breadth of between 10 and several hundred Angstroms.
Thermal-oxide-based tip sharpening is effective and is commonly employed in current silicon-based field emitter tip application methodologies. However, especially when used to sharpen silicon-based field emitter tips fabricated on the surface of CMOS wafers, the thermal oxidation tip sharpening process has clear deficiencies due to the relatively high temperatures, commonly greater than 900 C, necessary to grow the surface layer of SiO2. A first deficiency is that the underlying CMOS circuitry may employ low-melting-point conductors that can be degraded by high temperature exposure. Thus, extremely precise application of heat must be carried out to grow the surface layer of SIO2 while not adversely effecting underlying CMOS circuitry. Often, to increase physical stability of silicon-based field emitter tips, a thin, metallic layer is deposited on the silicon surface of the field emitter tip. A second deficiency of thermal-oxide-based tip sharpening is that, once the metal is deposited, high-temperature sharpening processes can no longer be employed without melting or vaporizing the deposited metal. For these reasons, designers and manufacturers of silicon-based field emitter tips have recognized the need for an economical, low-temperature process for sharpening silicon-based field emitter tips.
One embodiment of the present invention provides an efficient and economical process for sharpening silicon-based field emitter tips at low temperatures. A rough field emitter tip is carved out from a silicon well below a photoresist mask by isotropic plasma etching. The photoresist mask is removed, and the rough silicon-based field emitter tip that results is sharpened by isotropic xenon difluoride, XeF2 etching.